Print Print Send link Bookmark and Share

Wafer level heterogeneous integration

Thinned silicon wafer


VTT has about thirty years’ history in microelectronics research. Our present technology portfolio covers wafer thinning, chemical mechanical polishing, wafer bonding, cavity SOI wafers, flip chip bonding, fine pitch solder bumping, through-silicon vias, (3D) radiation detectors, integrated passive components including high-Q inductors, BiCMOS with several advanced process modules, such as high-voltage, non-volatile memory and integration with MEMS.


Our inspiration is to develop, for VTT’s customers and in our research projects, microelectronics solutions with unprecedented performance and reliability, and at a reasonable cost.


Innovative integration processes will address the challenges. For instance, the vertical integration with TSVs (through-silicon vias) allows devices to be integrated in systems with higher performance and reduced volume. Another example is the monolithic integration of the integrated circuit, and sensor or actuator elements with increased reliability and lower cost.


From the customer point of view, there are two benefits. On one hand, the availability of a rich technology portfolio as a one-stop shop, and on the other hand, our technology competence is combined with the skills of the application-oriented research teams.

References and merits

VTT has received several CERN Industrial awards for our contribution in the flip chip bonding of pixel detectors for the Large Hadron Collider experiment.

Our wafer bonding processes and our cavity SOI wafers have a worldwide reputation.

VTT is the coordinator of the FP6 RF-PLATFORM-project.

Double metal level Cu-coils

Additional information

Philippe Monnoyer
Head of Research Area
+358 20 722 4395